In general, a memory device is supplied with an external voltage (VDD) and a ground voltage (VSS) and generates and uses internal voltages necessary for internal operations. The internal voltages necessary for the internal operations of a memory device include a core voltage (Vcore) to be supplied to a memory core region, a high voltage (Vpp) to be used upon driving of a word line or overdriving, and a low voltage (Vbb) to be supplied as a bulk voltage of an NMOS transistor of a core region. A voltage monitoring test circuit is used to monitor these various internal voltages.
FIG. 1 is a block diagram illustrating the configuration of a conventional voltage monitoring test circuit.
The conventional voltage monitoring test circuit includes a voltage generation unit 11, a transmission unit 12 and a voltage sensing pad unit 13.
The voltage generation unit 11 includes first to fourth voltage generating sections 111 to 114 and generates first to fourth voltages VOL<1:4>. The transmission unit 12 includes first to fourth transmitting sections 121 to 124 and transmits the first to fourth voltages VOL<1:4> to the voltage sensing pad unit 13 in response to first to fourth switching signals SW<1:4>. The voltage sensing pad unit 13 receives the first to fourth voltages VOL<1:4> and outputs the first to fourth voltages VOL<1:4>.
Referring to FIG. 2, the first to fourth switching signals SW<1:4> are sequentially enabled to logic high levels. The first to fourth transmitting sections 121 to 124 sequentially transmit the first to fourth voltages VOL<1:4> to the voltage sensing pad unit 13 in response to such first to fourth switching signals SW<1:4>.
Since there is a period (hereinafter, referred to as a ‘transition period’) in which enable periods of the first to fourth switching signals SW<1:4> overlap with each other, short circuits occur in the first to fourth voltage generating sections 111 to 114. For example, in a transition period TRN1 in which the enable periods of the first switching signal SW<1> and the second switching signal SW<2> overlap with each other, a short circuit occurs between the first voltage generating section 111 and the second voltage generating section 112.
Further, when the voltage monitoring test circuit monitors a voltage, because charges remain in the voltage sensing pad unit 13, the first to fourth voltages VOL<1:4> cannot be precisely monitored. For example, when the voltage monitoring test circuit monitors the second voltage VOL<2> in response to the second switching signal SW<2>, because charges generated by a previously monitored first voltage VOL<1> may remain in the voltage sensing pad unit 13 for a certain period, monitoring of the second voltage VOL<2> may be affected by the first voltage VOL<1> that remains in the voltage sensing pad unit 13. Consequently, the second voltage VOL<2> cannot be precisely monitored.
Therefore, in the conventional voltage monitoring test circuit, since transition periods exist, short circuits occur between the first to fourth voltage generating sections 111 to 114, and since charges remain in the voltage sensing pad unit 13, the first to fourth voltages VOL<1:4> cannot be precisely monitored.